Multiple stabilized DC power supply circuits are applied in portable electronic devices, as well as other so-called electronic equipments. Power supply circuits whose characteristics adapt to different purposes are used for digital circuits, high-frequency circuits, analog circuits, and the like. In case of a cellular phone, a very high power supply ripple rejection is required for a RF transmitting circuit because poor ripple rejection results in poor clearness of voice conversation. Power supply ripple noise has a detrimental effect on the error rate, even in the case of wireless communications means whereby information is converted to digital code and transmitted and received, because the carrier signals are subjected to analog modulation and demodulation during transmission and reception. An operating current of 100 μA, which is sufficient for realizing a ripple elimination rate, for instance, of −80 db, is possible with conventional portable telephones. However, the newest trend in portable telephones is the improvement of overall power supply efficiency by splitting the inside of the device into many blocks and supplying power to each block, in order to prolong battery life. In short, the newest trend in portable telephones involves a plurality of power supply circuits loaded in one device so that the operating current of each power supply circuit is strictly curtailed.
It is estimated that several billion electronic devices operate throughout the world today. In this connection, assuming that one power supply circuit operates at 200 μA, a current of 1,000 kA is passed by 5 billion circuits, and assuming that these operate at 3 V, 3,000 kW of power are being consumed.
The prior art and the circuit theory on which this art is based are described below with reference to the figures.
(1) Example of Conventional Circuit
FIG. 1 shows a block diagram of a conventional DC power supply circuit with adaptively controlled bias. FIG. 2 shows a circuit diagram of a conventional DC power supply circuit with adaptively controlled bias. Vdd (VDD) and Vss (VSS) in FIG. 1 are the power supply terminals.
The conventional DC power supply circuit with adaptively controlled bias shown in FIGS. 1 and 2 comprises a differential amplifier U41, an output amplifier U42, an output voltage dividing circuit U43, a reference voltage circuit U44, and a bias current boost circuit U45.
Differential amplifier U41 operates such that it amplifies the difference in voltage between reference voltage circuit U44 and voltage dividing circuit U43 and applies that voltage to output circuit U42 to control an output transistor P43 of output circuit U42 and causes a constant output voltage Vout to be output. RL in FIGS. 1 and 2 is a load resistance. Load resistance RL takes in a current of several 100 mA. Moreover, C3 is an output decoupling capacitor. Together with an equivalent series resistance Resr, output decoupling capacitor C3 participates closely in the stabilization of this DC power supply circuit. Bias current boost circuit U45 operates such that it increases the operating bias current of differential amplifier U41 when load current first begins to flow and thus improves the stability, the response speed, and the ripple noise elimination rate. In essence, when no load current is flowing to the power supply circuit, the system operates at the minimum operating current, and when load current is flowing, the bias current is increased and a stable, efficient operation of the power supply circuit is realized. The load current at which the boost starts is settable by the size ratio between transistor P45 and N47, and is usually set to a small load current region that is not frequently used.
(2) Theoretical Explanation of Conventional Circuit
The output voltage will now be subjected to theoretical study. Output voltage Vout is represented by the following formula.Vout=Vref ×(Av/1+K×Av)+S0  (1)Where, Vref is the reference voltage, AV is the voltage gain of differential amplifier U41, K is the voltage dividing ratio of voltage dividing circuit U43, and S0 is the system offset voltage of differential amplifier U41.
Reference voltage Vref is affected by changes in power supply voltage VDD; therefore, the percentage change thereof is represented by the power supply voltage coefficient of Vref, or ΔVref=(δVref/δv)/K.
K is the voltage dividing ratio of the output voltage dividing resistance; therefore, K<1, and unless ripple ΔVref that accompanies Vref is eliminated by a filter, it is impossible to obtain a good PSPR (power supply rejection ratio; this is the ratio at which the output has changed when the power supply has changed by, for instance, 1V. For example, if the output changes by 1 mV, PSPR becomes 1 mV/1V, in essence, −60 dB.). However, the ripple of Vref is contained in frequencies ranging from very low to high frequencies; therefore, a large time constant is needed for filtering, and it is impossible to integrate filters for eliminating ripple over the entire frequency range on the same semiconductor chip.
The voltage dividing ratio K is represented by the following formula:K=R1/R1+R2When each resister R1 and R2 is fabricated with a poly silicon material, the supply voltage dependency is negligible small. Therefore, it is assumed that the percentage change in the VDD is not taken into consideration. The value of K is the voltage dividing value that determines the output voltage. Vref is generally from 0.2 to 0.8; therefore, very small values and very large values is not settable. Therefore it contributes to ripple rejection slightly.
S0 in formula (1) represents the system-offset voltage and is inevitable because of the circuit structure. S0 is a new concept that was assumed to be present based on experimental values. It has been experimentally shown that VDD does have an effect, and generally has a positive coefficient. However, making this coefficient a negative value has an important effect on formula (1).
The power supply voltage coefficient ΔS0 of S0 is represented by ΔS0=δS0/δv.
Av is the open loop gain under the amplification rate of the entire circuit, and is, of course, dependent on the power supply voltage VDD; therefore, the percentage change is represented by the following differential equation:Av=(δAv/δv)/(1+KAv)2.
The ripple component is represented by the following formula (2):ΔVout=ΔVref+Vref×Av+ΔS0  (2)Voltage gain AV will now be subjected to theoretical study.
Differential amplifier U41 in FIG. 2 is divided into first amplification circuit U41-1 and second amplification circuit U41-2, and output amplification circuit U42 is regarded as the third amplification circuit. The voltage gain of the first, second, and third amplification circuits is Av1, Av2, and Av3, respectively.
The power supply gain Av is represented by Av=Av1×Av2×Av3.
The power supply gain Avi of the ith amplification circuit is represented by Avi=Gmi×Zoi.
Here, Gmi and Zoi represent the conductance and output impedance of the ith amplification circuit.
Output impedance Zoi is equal to the parallel impedance of output resistance Rpi of the P channel FET of the ith amplification circuit, output resistance Rni of the N channel FET of the ith amplification circuit, and the capacity component Coi of the output of the ith amplification circuit. In the case of the circuit structure shown in FIG. 2, P41 and P42 pertain to the P channel FET of the first amplification circuit U41-1, and N41 pertains to the N channel FET of the first amplification circuit U41-1. Similarly, P44 pertains to the P channel FET of the second amplification circuit U41-2, and N44 pertains to the N channel FET of the second amplification circuit U41-2. Moreover, P43 pertains to the P channel FET of the third amplification circuit U42.
The output resistance Rpi of the P channel FET of the ith amplification circuit is represented by formula (3).Rpi=α(Li/Idi)√(Vgdi+Vtpi)  (3)
Here, α is the correction coefficient. The value of α is generally 5×106 √V/M.
The conductance Gmi of the ith amplification circuit is represented by formula (4).Gmi=√{2μp Cox(Wi/Li)Idi}  (4)Here, μp, Cox, Wi, Li, and Idi are the P channel FET carrier mobility, gate oxide film unit capacity, and transistor i channel width, channel length, and drain current.
The frequency characteristics will now be discussed.
The first, second, and third amplification circuits have a pole at a frequency Fpi represented by formula (5).Fpi=1/2π×Zoi  (5)
The gain of the amplification circuit of each stage begins to roll-off by a ratio of −6 db/octave and the phase delay appears at the pole frequency Fpi.
It is clear from the results of the above-mentioned that according to formulas (3) and (4) with respect to the output resistance Rpi and the conductance Gmi, the gain increases with an increase in the operating current Idi of each amplification circuit, and that the desired characteristics are obtained with respect to the ripple elimination rate from formula (1). Moreover, according to formulas (5) and (3), the pole frequency Fpi increases with an increase in the operating current IDi and is settable freely, and the phase can be delayed to improve stability. In short, as a result, the desired characteristics with respect to a stabilized DC power supply are obtained with a higher operating current Idi.
However, increasing the operating current limitlessly, the larger total current consumption of the equipment leads to a reduction in battery life and a reduction in energy efficiency. Thus, there is a huge need for a bias current boost-type power supply circuit with which the operating current decreases at no load and the operating current increases at loaded.
(3) Problems with the Prior Art
Many technologies for adaptive control of bias current have been proposed. Examples of patent references relating to this type of technology are JP Unexamined Patent Publication (Kokai) 2001-75,663, JP Unexamined Patent Publication (Kokai) 2001-34,351, JP Unexamined Patent Publication (Kokai) 3-158,912, and U.S. Pat. No. 6,522,111 B2.
The basic structure of a conventional adaptive control circuit as cited in these references is one wherein the voltage output of an error amplifier is converted to current, and fed back as a control current proportional to the output current. A major problem with these conventional adaptive control circuits is the unstable operation or oscillation caused by positive feedback. A feedback circuit having a positive feedback loop oscillates when the gain of the feedback loop is 1 or higher. None of the prior technologies cited in the above-mentioned references solves this essential problem. Conditions under which oscillation occurs are present in each of the prior technologies and none can be put to practical use.
FIG. 3 is a graph showing the results of a simulation of the phase gain curve of the bias current feedback loop under various loads. Specifically, the results are from an AC analysis when the P45 gate of the circuit in FIG. 2 was AC blocked. Gain curves 100, 101, and 102 and phase curves 103, 104, and 105 in FIG. 3 represent the curves when the load resistance RL is 200, 500, and 5 kΩ respectively. Curve 101 exceeds a gain of 1 and the phase of curve 104 changes by 180° or more; therefore, it is clear that conditions under which oscillation occurs are generated. The above-mentioned oscillation condition shifts when the circuit constant in FIG. 2 is changed. Incidentally, the oscillation condition shifts in the direction of a large load current as the channel length of P45 increases. The range of the oscillation condition becomes broader with a reduction in the capacity of output capacitor C3.
FIG. 4 is the waveform diagram showing the results of a transient response analysis from the input power supply. FIG. 4 shows that in the transient response analysis, the output PD node of differential amplifier U41 oscillates under a frequency near the peak of gain curve 101. The conventional circuit in FIG. 2 always exhibits unstable operating conditions in response to load current unless the gain of the feedback loop is 1 or less. It is a self-evident that when the gain of the feedback loop is 1 or less, the original bias current boost function is lost, which is the same as having no boost circuit.
FIG. 5 is another conventional example of a DC power supply circuit with adaptively controlled bias. This example differs from the structure of the power supply circuit in FIG. 2 in that differential amplifier U51 consists of one differential circuit. Differential amplifier U51 comprises fewer amplification steps; therefore, the gain of the feedback loop can be set smaller and the oscillation condition can be reduced, although it cannot be completely eliminated. In contrast to the example in FIG. 2, the range of the oscillation condition becomes broader as the output capacitor C3 becomes larger.